npn silicon transistor maximum ratings rating symbol value unit collector-emitter voltage v ceo 300 vdc collector-base voltage v cbo 300 vdc collector-emitter voltage v cer 300 vdc emitter-base voltage v ebo 5.0 vdc collector current i c 100 madc total power dissipation up to t a = 25 c p d 1.5 watts storage temperature range t stg 65 to +150 c junction temperature t j 150 c device marking dc thermal characteristics characteristic symbol max unit thermal resistance from junction-to-ambient (1) r q ja 83.3 c/w electrical characteristics (t a = 25 c unless otherwise noted) characteristics symbol min max unit off characteristics collector-emitter breakdown voltage (i c = 1.0 madc, i b = 0) v (br)ceo 300 e vdc collector-base breakdown voltage (i c = 100 m adc, i e = 0) v (br)cbo 300 e vdc collector-emitter breakdown voltage (i c = 100 m adc, r be = 2.7 k w ) v (br)cer 300 e vdc emitter-base breakdown voltage (i e = 10 m adc, i c = 0) v (br)ebo 5.0 e vdc collector-base cutoff current (v cb = 200 vdc, i e = 0) i cbo e 10 nadc collectoremitter cutoff current (v ce = 250 vdc, r be = 2.7 k w ) (v ce = 200 vdc, r be = 2.7 k w , t j = 150 c) i cer e e 50 10 nadc m adc 1. device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 in 2 . preferred devices are on semiconductor recommended choices for future use and best overall value. on semiconductor ? semiconductor components industries, llc, 2001 november, 2001 rev. 5 1 publication order number: bf720t1/d bf720t1 npn silicon transistor surface mount on semiconductor preferred device case 318e-04, style 1 sot223 (to-261aa) 1 2 3 4 collector 2,4 base 1 emitter 3
bf720t1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) (continued) characteristic symbol min max unit on characteristics dc current gain (i c = 25 madc, v ce = 20 vdc) h fe 50 e e collector-emitter saturation voltage (i c = 30 madc, i b = 5.0 madc) v ce(sat) e 0.6 vdc dynamic characteristics currentgain e bandwidth product (i c = 10 madc, v ce = 10 vdc, f = 35 mhz) f t 60 e mhz feedback capacitance (v ce = 30 vdc, i c = 0, f = 1.0 mhz) c re e 1.6 pf figure 1.
bf720t1 http://onsemi.com 3 c, capacitance (pf) figure 1. dc current gain v r , reverse voltage (volts) 0.1 100 0.1 10 1.0 10 1000 c eb @ 1mhz figure 2. capacitance i c , collector current (ma) 100 70 50 30 20 10 7.0 5.0 3.0 2.0 80 70 50 30 20 10 t j = 25 c v ce = 20 v f = 20 mhz f, current-gain bandwidth (mhz) t 1.0 i c , collector current (ma) figure 3. currentgain bandwidth v, voltage (volts) 1.4 0.0 1.2 1.0 0.8 0.6 0.4 0.2 100 10 0.1 1.0 100 1.0 c cb @ 1mhz 60 40 v be(on) @ 25 c, v ce = 10 v v ce(sat) @ 25 c, i c /i b = 10 v be(sat) @ 25 c, i c /i b = 10 v ce(sat) @ 125 c, i c /i b = 10 v ce(sat) @ -55 c, i c /i b = 10 v be(sat) @ 125 c, i c /i b = 10 v be(sat) @ -55 c, i c /i b = 10 v be(on) @ 125 c, v ce = 10 v v be(on) @ -55 c, v ce = 10 v figure 4. aono voltages i c , collector current (ma) 120 0.1 1.0 10 100 80 60 0 h fe , dc current gain t j = +125 c 25 c -55 c v ce = 10 vdc 100 20 40
bf720t1 http://onsemi.com 4 p d = t j(max) t a r q ja p d = 150 c 25 c 83.3 c/w = 1.50 watts information for using the sot223 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection sot223 power dissipation the power dissipation of the sot223 is a function of the pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . us- ing the values provided on the data sheet for the sot223 package, p d can be calculated as follows. the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 1.5 watts. interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 mm inches 0.091 2.3 sot223 0.8 watts 1.25 watts* 1.5 watts r , thermal resistance, junction to ambient (c/w) q ja a, area (square inches) 0.0 0.2 0.4 0.6 0.8 1.0 160 140 120 100 80 figure 5. thermal resistance versus collector pad area for the sot-223 package (typical) board material = 0.0625 g10/fr4, 2 oz copper t a = 25 c *mounted on the dpak footprint the 83.3 c/w for the sot-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. there are other alternatives to achieving higher power dissipation from the sot-223 package. one is to increase the area of the collector pad. by increasing the area of the collector pad, the power dissipation can be increased. although the power dissipation can almost be another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. a graph of r q ja versus collec- tor pad area is shown in figure 5.
bf720t1 http://onsemi.com 5 ? the soldering temperature and time should not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient should be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference should be a maximum of 10 c. for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 7 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. a solder stencil is required to screen the optimum amount of solder paste onto the footprint. the stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. the stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. typical solder heating profile the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
bf720t1 http://onsemi.com 6 step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 140 c figure 6. typical solder heating profile desired curve for high mass assemblies 170 c
bf720t1 http://onsemi.com 7 package dimensions to-261aa style 1: pin 1. base 2. collector 3. emitter 4. collector h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 case 318e04 issue h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch.
bf720t1 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. bf720t1/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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